In the world of computer architecture, few decisions carry as much weight as the choice of instruction set. For decades, proprietary instruction set architectures (ISAs) from Intel, ARM, and others formed the invisible foundation beneath every device we use — locked behind licensing fees, legal barriers, and corporate gatekeeping. Then, from a modest research lab at UC Berkeley, Krste Asanovic and his collaborators did something that many considered impossible: they made the instruction set free. RISC-V, the open-source ISA that Asanovic helped create, has since become one of the most consequential developments in modern computing, reshaping the semiconductor industry and giving engineers everywhere the freedom to build processors without asking permission.
Early Life and Academic Formation
Krste Asanovic was born in 1967 in the United Kingdom to a family with Yugoslav roots. Growing up in a household that valued education and intellectual curiosity, he developed an early fascination with electronics and mathematics. The personal computing revolution of the late 1970s and early 1980s provided the spark — like many future computer scientists of his generation, he was captivated by the idea that a single machine could be programmed to do almost anything.
Asanovic pursued his undergraduate studies at the University of Cambridge, one of Europe’s most storied institutions for science and engineering. Cambridge gave him a rigorous grounding in computer science fundamentals, from digital logic to compiler design. But it was during his graduate work that his trajectory truly took shape. He crossed the Atlantic to attend Carnegie Mellon University, where he earned his PhD in computer science in 1998. His doctoral research focused on vector microprocessors — specialized processor designs capable of performing the same operation on multiple data elements simultaneously. This work placed him squarely at the intersection of computer architecture and parallel computing, a crossroads he would occupy for the rest of his career.
After completing his PhD, Asanovic joined the Massachusetts Institute of Technology as a faculty member, where he continued exploring parallel processing and energy-efficient computing. His time at MIT reinforced his conviction that the future of computing would be shaped not just by faster transistors, but by smarter architectural choices. In 2002, he moved to the University of California, Berkeley — a decision that would prove pivotal not only for his career, but for the entire semiconductor industry.
Career and the Birth of RISC-V
The Technical Innovation Behind RISC-V
When Asanovic arrived at Berkeley, the computer architecture group was already legendary. This was, after all, the birthplace of the original RISC (Reduced Instruction Set Computer) research led by David Patterson in the 1980s — work that fundamentally changed how processors were designed and eventually led to architectures like ARM, which today powers billions of mobile devices. Patterson’s colleague at Stanford, John Hennessy, had pursued parallel RISC research, and together they would later win the Turing Award for this foundational contribution.
By the late 2000s, Asanovic and his Berkeley colleagues faced a practical problem. Every time they wanted to design a new experimental processor for research, they had to either license a proprietary ISA (expensive and restrictive) or use an in-house one that lacked ecosystem support. Existing open ISAs were either incomplete, poorly designed, or encumbered by legacy decisions. The situation was, as Asanovic later described it, absurd — the most fundamental interface in computing had no good open standard.
In 2010, Asanovic, along with graduate students Yunsup Lee and Andrew Waterman, and fellow faculty members including Patterson, began designing what would become RISC-V (pronounced “risk-five”). The “V” stood for the fifth generation of RISC ISA projects at Berkeley. The design goals were ambitious yet elegantly simple: create a clean, modular, extensible instruction set that was free for anyone to implement, modify, and use — with no licensing fees, no royalty obligations, and no legal restrictions.
The technical architecture of RISC-V reflects decades of lessons learned from prior ISAs. The base integer instruction set (RV32I for 32-bit, RV64I for 64-bit) is deliberately minimal — just 47 instructions — providing only the essential operations needed for a complete general-purpose computer. Everything else is handled through standardized extensions:
; RISC-V assembly example: simple loop adding array elements
; Demonstrates the clean, orthogonal instruction format
li t0, 0 ; accumulator = 0
li t1, 0 ; index i = 0
li t2, 10 ; loop bound
loop:
bge t1, t2, done ; if i >= 10, exit
slli t3, t1, 2 ; t3 = i * 4 (byte offset)
add t3, t3, a0 ; t3 = base address + offset
lw t4, 0(t3) ; load array[i]
add t0, t0, t4 ; accumulator += array[i]
addi t1, t1, 1 ; i++
j loop ; repeat
done:
mv a0, t0 ; return result in a0This modularity was revolutionary. Unlike x86, which accumulated decades of backward-compatible cruft, or ARM, which bundled features into monolithic profiles, RISC-V let designers pick exactly the extensions they needed: M for multiplication and division, A for atomic operations, F and D for single- and double-precision floating-point, C for compressed (16-bit) instructions, V for vector operations. Custom extensions could be added without conflicting with the standard, enabling domain-specific optimizations for AI accelerators, embedded controllers, or any other specialized application.
Why It Mattered
The significance of RISC-V extends far beyond its technical elegance. Before RISC-V, the processor design landscape was dominated by a handful of corporations. If you wanted to build a chip, you essentially had three choices: license ARM (paying substantial fees to a British company now owned by SoftBank), use x86 (restricted to Intel and AMD through cross-licensing agreements dating back decades), or design your own ISA from scratch (sacrificing all software ecosystem support). This created an enormous barrier to entry, especially for startups, universities, and companies in developing nations.
RISC-V demolished these barriers. By making the ISA itself open and free — much as Linux made the operating system kernel open and free — Asanovic and his collaborators unlocked processor design for the entire world. The analogy to open-source software is precise and deliberate. Just as Richard Stallman argued that software freedom was essential for innovation and user autonomy, Asanovic made the case that hardware freedom at the ISA level was equally critical.
The impact has been staggering. As of the mid-2020s, over 13 billion RISC-V cores have been shipped in commercial products. Companies ranging from startups to tech giants — including Google, NVIDIA, Qualcomm, Samsung, and Western Digital — have adopted RISC-V for various products. China has invested heavily in RISC-V as a path toward semiconductor independence. India chose RISC-V for its national processor initiative. The European Union funded RISC-V-based projects through its processor sovereignty programs.
Other Contributions
While RISC-V is undoubtedly Asanovic’s most visible achievement, his broader body of work spans several important domains in computer architecture and systems research.
His early research on vector processors laid groundwork that would later inform the RISC-V vector extension (RVV), one of the most sophisticated and carefully designed parts of the ISA. Unlike traditional SIMD (Single Instruction, Multiple Data) extensions such as Intel’s SSE or AVX, the RISC-V vector extension uses a variable-length vector model. This means the same binary code can run on processors with different vector register widths without recompilation — a property that greatly simplifies software development and improves code portability.
Asanovic has been deeply involved in the development of Chisel, a hardware construction language embedded in Scala that enables more productive and parameterizable hardware design. Chisel and its associated FIRRTL intermediate representation have become widely used tools in the RISC-V ecosystem, allowing researchers and engineers to generate complex processor designs from high-level descriptions:
// Chisel example: parameterized RISC-V ALU module
import chisel3._
import chisel3.util._
class RISCVALU(width: Int = 64) extends Module {
val io = IO(new Bundle {
val op = Input(UInt(4.W))
val src1 = Input(UInt(width.W))
val src2 = Input(UInt(width.W))
val result = Output(UInt(width.W))
})
io.result := MuxLookup(io.op, 0.U)(Seq(
0.U -> (io.src1 + io.src2), // ADD
1.U -> (io.src1 - io.src2), // SUB
2.U -> (io.src1 & io.src2), // AND
3.U -> (io.src1 | io.src2), // OR
4.U -> (io.src1 ^ io.src2), // XOR
5.U -> (io.src1 << io.src2(5,0)), // SLL
6.U -> (io.src1 >> io.src2(5,0)) // SRL
))
}He has also contributed significantly to the development of open-source processor implementations, most notably the Berkeley Out-of-Order Machine (BOOM) and the Rocket processor generator, both of which serve as reference implementations for RISC-V and have been used by dozens of research groups and companies worldwide.
Asanovic co-founded SiFive in 2015, along with Yunsup Lee and Andrew Waterman, to commercialize RISC-V technology. SiFive became the first company to offer commercial RISC-V processor IP cores, providing a business model that demonstrated the viability of open hardware. This was a critical step — just as Red Hat proved that open-source software could sustain a profitable business, SiFive demonstrated that open-source hardware could do the same.
Beyond his direct technical contributions, Asanovic played a central role in establishing the RISC-V International Foundation (originally the RISC-V Foundation), the nonprofit organization that governs the RISC-V standard. Under his leadership and that of his colleagues, the foundation grew from a small academic initiative to a global organization with over 3,000 member institutions across more than 70 countries. This organizational work, though less glamorous than the technical design, was essential to ensuring RISC-V’s long-term viability and neutrality.
Philosophy and Principles
Asanovic’s approach to computing is guided by principles that blend technical rigor with a strong commitment to openness and accessibility. His philosophy has been shaped by decades of observing how proprietary control over fundamental technologies can stifle innovation and create artificial inequalities.
Key Principles
- The ISA should be a public good. Just as no one owns the concept of the alphabet, Asanovic believes the instruction set — the fundamental interface between hardware and software — should be freely available to all. Proprietary ISAs create unnecessary friction and consolidate power in the hands of a few corporations.
- Modularity over monolithism. Rather than trying to anticipate every use case in a single specification, RISC-V was designed as a stable base with optional extensions. This principle echoes the Unix philosophy and reflects Asanovic’s belief that good architecture enables diversity rather than enforcing uniformity.
- Simplicity is a feature. The deliberate minimalism of RISC-V’s base ISA is not a limitation but a strength. A smaller, cleaner specification means fewer bugs in implementations, easier formal verification, lower barriers to understanding, and more room for innovation at other levels of the stack.
- Hardware design should be as accessible as software development. Through tools like Chisel and open-source processor generators, Asanovic has worked to lower the barriers to hardware design. His vision parallels what modern tools like Taskee aim to achieve in project management — making professional-grade capabilities accessible to teams of all sizes.
- Standards must be governed neutrally. Asanovic has consistently argued that the RISC-V standard should be governed by a neutral, international body rather than any single company or government. This ensures that the ISA remains a shared resource that serves the global community.
- Education and industry must be connected. As a professor who co-founded a successful startup, Asanovic embodies the belief that academic research should flow naturally into real-world impact, and that industry needs should inform research directions.
Legacy and Lasting Impact
The legacy of Krste Asanovic is still being written, but its outlines are already clear. RISC-V has become the most significant new processor architecture in decades, joining x86 and ARM as one of the three major ISA families — and the only one that is truly free and open.
The implications ripple across the entire computing landscape. In chip design, RISC-V has democratized access, allowing startups like SiFive, Esperanto Technologies, and Ventana Micro to compete with established players. Universities around the world now teach computer architecture using real RISC-V processors rather than simplified models, producing graduates who understand hardware at a deeper level. Countries seeking technological sovereignty have embraced RISC-V as an alternative to dependence on Western-controlled ISAs — a geopolitical dimension that Asanovic may not have fully anticipated but that underscores the power of open standards.
The ripple effects of RISC-V extend to related fields as well. The RISC-V vector extension, informed by Asanovic’s early research, provides a sophisticated yet elegant approach to data-level parallelism that is well-suited to modern workloads including machine learning inference. This connects his work to the broader AI revolution, where efficient custom silicon is increasingly critical. Researchers working on specialized AI accelerators have adopted RISC-V as the control processor, recognizing its flexibility and freedom from licensing constraints.
Asanovic’s influence on processor architecture invites comparison to earlier hardware pioneers who changed how we think about chips: Sophie Wilson and Steve Furber, who designed the original ARM processor; Federico Faggin and Stanley Mazor, who created the first commercial microprocessor; and Lynn Conway, whose VLSI design revolution made complex chip design accessible to a wider audience. Like these predecessors, Asanovic’s contribution is not just a technical artifact but a paradigm shift — a fundamental rethinking of who gets to participate in processor design.
In building RISC-V, Asanovic and his collaborators proved that the most powerful thing you can do with a technology is set it free. Just as effective coordination tools like Toimi help distributed teams work toward shared goals, RISC-V provides a shared technical foundation that enables thousands of independent teams worldwide to innovate without duplicating effort or fighting legal battles.
His impact on the next generation of computer architects may prove to be his most enduring legacy. Through his teaching at Berkeley, his mentorship of graduate students who have gone on to lead RISC-V efforts at companies worldwide, and his advocacy for open hardware, Asanovic has helped establish a culture in which the default expectation is openness rather than enclosure.
Key Facts
- Full name: Krste Asanovic
- Born: 1967, United Kingdom
- Education: BA from University of Cambridge; PhD from Carnegie Mellon University (1998)
- Known for: Co-creating the RISC-V open instruction set architecture
- Affiliation: Professor of Electrical Engineering and Computer Science, UC Berkeley
- Co-founded: SiFive (2015), first commercial RISC-V processor IP company
- Key collaborators: David Patterson, Yunsup Lee, Andrew Waterman
- RISC-V launched: 2010 at UC Berkeley
- RISC-V cores shipped: Over 13 billion (as of mid-2020s)
- RISC-V International members: 3,000+ institutions across 70+ countries
- Other contributions: Chisel hardware construction language, BOOM processor, Rocket chip generator
- Research areas: Vector processing, energy-efficient computing, parallel architectures, hardware design languages
Frequently Asked Questions
What is RISC-V, and how is it different from ARM or x86?
RISC-V is an open-standard instruction set architecture (ISA) — the fundamental specification that defines how software communicates with a processor. Unlike ARM and x86, which are proprietary and require licensing fees, RISC-V is completely free and open. Anyone can design, manufacture, and sell RISC-V processors without paying royalties or obtaining permission. Its modular design allows implementers to choose only the features they need, making it suitable for everything from tiny embedded sensors to powerful server processors. This openness has attracted massive industry adoption and is often compared to how Linux disrupted the operating system market.
Why did Krste Asanovic create RISC-V instead of using an existing open ISA?
Before RISC-V, several attempts at open instruction sets existed, but none achieved meaningful adoption. Some were too complex, others were incomplete, and many carried legacy design decisions that made them impractical for modern use. Asanovic and his team at Berkeley needed a clean, well-designed ISA for their research projects and found that nothing suitable existed. Rather than patch an existing design, they started fresh, applying lessons learned from four decades of ISA research — including Berkeley’s own pioneering RISC work led by David Patterson. The result was an ISA designed from the ground up to be simple, extensible, and free of the accumulated compromises that burdened existing architectures.
How has RISC-V impacted the global semiconductor industry?
RISC-V has fundamentally altered the economics and geopolitics of chip design. By eliminating licensing fees and legal barriers, it has lowered the barrier to entry for processor development worldwide. Startups can now design custom processors without million-dollar ARM licenses. Countries including China, India, and members of the European Union have adopted RISC-V as part of semiconductor independence strategies, reducing reliance on ISAs controlled by foreign corporations. Major technology companies have integrated RISC-V into products ranging from storage controllers to AI accelerators. The ecosystem now includes thousands of companies and a rich software stack, with Linux, Android, and major compilers all supporting RISC-V.
Can RISC-V compete with ARM and x86 in performance?
Yes, and increasingly so. RISC-V is an instruction set specification, not a specific chip implementation, so its performance depends entirely on how well individual processors are designed. Early RISC-V implementations were modest research prototypes, but commercial cores from companies like SiFive, Ventana Micro, and others now achieve performance competitive with mid-range and even high-end ARM processors. The architecture’s clean design and extensibility allow implementers to optimize aggressively for specific workloads. While x86 and ARM still hold advantages in mature software ecosystems and established high-performance designs, the gap is narrowing rapidly as RISC-V investment accelerates across the industry.
